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https://github.com/matrix-construct/construct
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50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
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// Matrix Construct
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//
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// Copyright (C) Matrix Construct Developers, Authors & Contributors
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// Copyright (C) 2016-2022 Jason Volk <jason@zemos.net>
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice is present in all copies. The
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// full license for this software is available in the LICENSE file.
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#pragma once
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#define HAVE_IRCD_SIMT_HWID2_H
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/// HW_ID2 Register
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struct ircd_simt_hwid2
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{
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uint
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queue, ///< Queue ID (shader stage).
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pipl, ///< Pipeline ID.
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me, ///< Micro-engine ID: 0 = graphics, 1 & 2 = ACE compute
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state, ///< State context ID.
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wg, ///< Work-group ID within the WGP.
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vm; ///< Virtual Memory ID.
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};
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/// Query hardware identification attributes
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inline struct ircd_simt_hwid2
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__attribute__((always_inline))
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ircd_simt_hwid2()
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{
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uint val = 0;
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#if defined(__AMDDNA__)
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asm volatile
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(
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"s_getreg_b32 %0, hwreg(HW_REG_HW_ID2, 0, 32)"
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: "=s" (val)
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);
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#endif
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return (struct ircd_simt_hwid2)
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{
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.queue = (val >> 0) & 0x0f,
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.pipl = (val >> 4) & 0x03,
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.me = (val >> 8) & 0x03,
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.state = (val >> 12) & 0x07,
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.wg = (val >> 16) & 0x1f,
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.vm = (val >> 24) & 0x0f,
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};
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}
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