From 1f87668a28bb26740398104a2bea6a9026be0c52 Mon Sep 17 00:00:00 2001
From: Jason Volk <jason@zemos.net>
Date: Thu, 1 Dec 2022 19:22:11 +0000
Subject: [PATCH] ircd::simt: Add cycles_rtc() intrinsic for s_memrealtime on
 (AMDGCN).

---
 include/ircd/simt/cycles.h | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/include/ircd/simt/cycles.h b/include/ircd/simt/cycles.h
index 2a770e1cd..2f7fcc84c 100644
--- a/include/ircd/simt/cycles.h
+++ b/include/ircd/simt/cycles.h
@@ -24,3 +24,29 @@ ircd_simt_cycles()
 	#endif
 }
 #endif
+
+#if defined(__OPENCL_VERSION__)
+/// Read the realtime-clock cycle counting timestamp `s_memrealtime` otherwise
+/// falls back to the default cycle counter (which defaults to zero if also not
+/// supported).
+///
+/// This is more consistent than `s_memtime` but slightly less granular; it is
+/// probably provided by a control unit rather than directly in an SIMD/ALU.
+inline ulong
+__attribute__((always_inline))
+ircd_simt_cycles_rtc()
+{
+	ulong ret;
+	#if defined(__AMDGCN__)
+		asm volatile
+		(
+			"s_memrealtime %0"
+			: "=s" (ret)
+		);
+	#else
+		ret = ircd_simt_cycles();
+	#endif
+
+	return ret;
+}
+#endif