ircd::simt: Add hardware ident access register (AMDDNA)

include/ircd/simt/hwid1.h

@@ -0,0 +1,51 @@
+// Matrix Construct
+//
+// Copyright (C) Matrix Construct Developers, Authors & Contributors
+// Copyright (C) 2016-2022 Jason Volk <jason@zemos.net>
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice is present in all copies. The
+// full license for this software is available in the LICENSE file.
+
+#pragma once
+#define HAVE_IRCD_SIMT_HWID1_H
+
+/// HW_ID1 Register
+struct ircd_simt_hwid1
+{
+	uint
+	wave,    ///< Wave ID within SIMD.
+	simd,    ///< SIMD within WGP: [0] = row, [1] = col
+	wgd,     ///< Workgroup Processor ID (distance from SPI)
+	wgt,     ///< Workgroup Processor ID (tier above/below SPI)
+	sa,      ///< Shader Array within SE.
+	se,      ///< Shader Engine ID.
+	dpr;     ///< Double-precision float units per SIMD.
+};
+
+/// Query hardware identification attributes
+inline struct ircd_simt_hwid1
+__attribute__((always_inline))
+ircd_simt_hwid1()
+{
+	uint val = 0;
+	#if defined(__AMDDNA__)
+	asm volatile
+	(
+		"s_getreg_b32 %0, hwreg(HW_REG_HW_ID1, 0, 32)"
+		: "=s" (val)
+	);
+	#endif
+
+	return (struct ircd_simt_hwid1)
+	{
+		.wave   = (val >> 0)  & 0x1f,
+		.simd   = (val >> 8)  & 0x03,
+		.wgd    = (val >> 10) & 0x07,
+		.wgt    = (val >> 13) & 0x01,
+		.sa     = (val >> 16) & 0x01,
+		.se     = (val >> 18) & 0x07,
+		.dpr    = (val >> 29) & 0x07,
+	};
+}

include/ircd/simt/hwid2.h

@@ -0,0 +1,49 @@
+// Matrix Construct
+//
+// Copyright (C) Matrix Construct Developers, Authors & Contributors
+// Copyright (C) 2016-2022 Jason Volk <jason@zemos.net>
+//
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice is present in all copies. The
+// full license for this software is available in the LICENSE file.
+
+#pragma once
+#define HAVE_IRCD_SIMT_HWID2_H
+
+/// HW_ID2 Register
+struct ircd_simt_hwid2
+{
+	uint
+	queue,   ///< Queue ID (shader stage).
+	pipl,    ///< Pipeline ID.
+	me,      ///< Micro-engine ID: 0 = graphics, 1 & 2 = ACE compute
+	state,   ///< State context ID.
+	wg,      ///< Work-group ID within the WGP.
+	vm;      ///< Virtual Memory ID.
+};
+
+/// Query hardware identification attributes
+inline struct ircd_simt_hwid2
+__attribute__((always_inline))
+ircd_simt_hwid2()
+{
+	uint val = 0;
+	#if defined(__AMDDNA__)
+	asm volatile
+	(
+		"s_getreg_b32 %0, hwreg(HW_REG_HW_ID2, 0, 32)"
+		: "=s" (val)
+	);
+	#endif
+
+	return (struct ircd_simt_hwid2)
+	{
+		.queue  = (val >> 0)  & 0x0f,
+		.pipl   = (val >> 4)  & 0x03,
+		.me     = (val >> 8)  & 0x03,
+		.state  = (val >> 12) & 0x07,
+		.wg     = (val >> 16) & 0x1f,
+		.vm     = (val >> 24) & 0x0f,
+	};
+}

include/ircd/simt/simt.h

@@ -13,6 +13,8 @@
 
 #include "portable.h"
 #include "assert.h"
+#include "hwid2.h"
+#include "hwid1.h"
 #include "hwid.h"
 #include "cycles.h"
 #include "mem.h"