mirror of
https://github.com/matrix-construct/construct
synced 2024-06-23 20:38:20 +02:00
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
// Matrix Construct
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//
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// Copyright (C) Matrix Construct Developers, Authors & Contributors
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// Copyright (C) 2016-2022 Jason Volk <jason@zemos.net>
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice is present in all copies. The
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// full license for this software is available in the LICENSE file.
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#pragma once
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#define HAVE_IRCD_SIMT_HWID_H
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/// HW_ID Register (legacy)
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struct ircd_simt_hwid
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{
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uint
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wave, ///< Wave buffer slot number.
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simd, ///< SIMD assigned to within unit.
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pipl, ///< Pipeline from which wave dispatched.
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cu, ///< Compute Unit ID.
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sa, ///< Shader Array within engine.
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se, ///< Shader Engine ID.
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tg, ///< Thread-group ID.
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vm, ///< Virtual Memory ID.
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queue, ///< Queue from which wave was dispatched.
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state, ///< State ID (graphics only, not compute).
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me; ///< Micro-engine ID.
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};
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/// Query hardware identification attributes (legacy)
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inline struct ircd_simt_hwid
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__attribute__((always_inline))
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ircd_simt_hwid()
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{
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uint val = 0;
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#if defined(__AMDGCN__)
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asm volatile
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(
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"s_getreg_b32 %0, hwreg(HW_REG_HW_ID, 0, 32)"
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: "=s" (val)
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);
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#endif
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return (struct ircd_simt_hwid)
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{
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.wave = (val >> 0) & 0xf,
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.simd = (val >> 4) & 0x3,
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.pipl = (val >> 6) & 0x3,
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.cu = (val >> 8) & 0xf,
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.sa = (val >> 12) & 0x1,
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.se = (val >> 13) & 0x3,
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.tg = (val >> 16) & 0xf,
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.vm = (val >> 20) & 0xf,
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.queue = (val >> 24) & 0x7,
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.state = (val >> 27) & 0x7,
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.me = (val >> 30) & 0x3,
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};
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}
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