mirror of
https://github.com/matrix-construct/construct
synced 2024-06-23 20:38:20 +02:00
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
// Matrix Construct
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//
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// Copyright (C) Matrix Construct Developers, Authors & Contributors
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// Copyright (C) 2016-2022 Jason Volk <jason@zemos.net>
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice is present in all copies. The
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// full license for this software is available in the LICENSE file.
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#pragma once
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#define HAVE_IRCD_SIMT_HWID1_H
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/// HW_ID1 Register
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struct ircd_simt_hwid1
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{
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uint
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wave, ///< Wave ID within SIMD.
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simd, ///< SIMD within WGP: [0] = row, [1] = col
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wgd, ///< Workgroup Processor ID (distance from SPI)
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wgt, ///< Workgroup Processor ID (tier above/below SPI)
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sa, ///< Shader Array within SE.
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se, ///< Shader Engine ID.
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dpr; ///< Double-precision float units per SIMD.
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};
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/// Query hardware identification attributes
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inline struct ircd_simt_hwid1
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__attribute__((always_inline))
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ircd_simt_hwid1()
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{
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uint val = 0;
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#if defined(__AMDDNA__)
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asm volatile
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(
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"s_getreg_b32 %0, hwreg(HW_REG_HW_ID1, 0, 32)"
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: "=s" (val)
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);
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#endif
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return (struct ircd_simt_hwid1)
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{
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.wave = (val >> 0) & 0x1f,
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.simd = (val >> 8) & 0x03,
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.wgd = (val >> 10) & 0x07,
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.wgt = (val >> 13) & 0x01,
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.sa = (val >> 16) & 0x01,
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.se = (val >> 18) & 0x07,
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.dpr = (val >> 29) & 0x07,
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};
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}
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