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https://github.com/go-gitea/gitea
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b33078fa33
* Moved conf assets into options folder * Dropped old bindata * Started to integrate options bindata and accessors * Do not enforce a builtin app.ini * Replaced bindata calls with options * Dropped bindata task from makefile, it's the generate task now * Always embedd app.ini to provide sane config defaults * Use sane defaults for the configuration * Defined default value for SSH_KEYGEN_PATH * Dropped "NEVER EVER MODIFY THIS FILE" header from app.ini * Fixed new paths in latest test additions * Drop bindata with make clean task * Set more proper default values
36 lines
971 B
Text
36 lines
971 B
Text
# Waveform formats
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*.vcd
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*.vpd
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*.evcd
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*.fsdb
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# Default name of the simulation executable. A different name can be
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# specified with this switch (the associated daidir database name is
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# also taken from here): -o <path>/<filename>
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simv
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# Generated for Verilog and VHDL top configs
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simv.daidir/
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simv.db.dir/
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# Infrastructure necessary to co-simulate SystemC models with
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# Verilog/VHDL models. An alternate directory may be specified with this
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# switch: -Mdir=<directory_path>
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csrc/
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# Log file - the following switch allows to specify the file that will be
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# used to write all messages from simulation: -l <filename>
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*.log
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# Coverage results (generated with urg) and database location. The
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# following switch can also be used: urg -dir <coverage_directory>.vdb
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simv.vdb/
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urgReport/
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# DVE and UCLI related files.
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DVEfiles/
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ucli.key
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# When the design is elaborated for DirectC, the following file is created
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# with declarations for C/C++ functions.
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vc_hdrs.h
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