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gitea/options/gitignore/SynopsysVCS
Thomas Boerger b33078fa33 Bindata is optional and over-writable on restart (#354)
* Moved conf assets into options folder

* Dropped old bindata

* Started to integrate options bindata and accessors

* Do not enforce a builtin app.ini

* Replaced bindata calls with options

* Dropped bindata task from makefile, it's the generate task now

* Always embedd app.ini to provide sane config defaults

* Use sane defaults for the configuration

* Defined default value for SSH_KEYGEN_PATH

* Dropped "NEVER EVER MODIFY THIS FILE" header from app.ini

* Fixed new paths in latest test additions

* Drop bindata with make clean task

* Set more proper default values
2016-12-22 19:12:23 +01:00

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# Waveform formats
*.vcd
*.vpd
*.evcd
*.fsdb
# Default name of the simulation executable. A different name can be
# specified with this switch (the associated daidir database name is
# also taken from here): -o <path>/<filename>
simv
# Generated for Verilog and VHDL top configs
simv.daidir/
simv.db.dir/
# Infrastructure necessary to co-simulate SystemC models with
# Verilog/VHDL models. An alternate directory may be specified with this
# switch: -Mdir=<directory_path>
csrc/
# Log file - the following switch allows to specify the file that will be
# used to write all messages from simulation: -l <filename>
*.log
# Coverage results (generated with urg) and database location. The
# following switch can also be used: urg -dir <coverage_directory>.vdb
simv.vdb/
urgReport/
# DVE and UCLI related files.
DVEfiles/
ucli.key
# When the design is elaborated for DirectC, the following file is created
# with declarations for C/C++ functions.
vc_hdrs.h