MirrorHub/nixpkgs
0
0
Fork 0
mirror of https://github.com/NixOS/nixpkgs.git synced 2024-11-18 07:46:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

Merge pull request #15606 from dvc94ch/fpga-toolchain-updates

Browse source 
FPGA toolchain updates
This commit is contained in:
Moritz Ulrich 2016-05-28 15:41:10 +02:00
commit 7b2fab05f3
5 changed files with 28 additions and 21 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
pkgs/applications/science/electronics/verilator/default.nix
View file

@ -2,11 +2,11 @@
stdenv.mkDerivation rec { stdenv.mkDerivation rec {
name = "verilator-${version}"; name = "verilator-${version}";
version = "3.874"; version = "3.884";
src = fetchurl { src = fetchurl {
url = "http://www.veripool.org/ftp/${name}.tgz"; url = "http://www.veripool.org/ftp/${name}.tgz";
sha256 = "070binwp0jnashi6w45km26vrn6200b8hdg4179lcqyzdxi8c06j"; sha256 = "1j159dg7m2ych5lwglb1qq1fgqh3kwhaa1r3jx84qdisg0icln2y";
}; };
enableParallelBuilding = true; enableParallelBuilding = true;

20
pkgs/applications/science/electronics/verilog/default.nix
View file

@ -1,14 +1,22 @@
{stdenv, fetchurl, gperf, flex, bison}: { stdenv, fetchFromGitHub, autoconf, gperf, flex, bison }:
stdenv.mkDerivation rec { stdenv.mkDerivation rec {
name = "verilog-0.9.7"; name = "iverilog-${version}";
version = "2016.05.21";
src = fetchurl { src = fetchFromGitHub {
url = "mirror://sourceforge/iverilog/${name}.tar.gz"; owner = "steveicarus";
sha256 = "0m3liqw7kq24vn7k8wvi630ljz0awz23r3sd4rcklk7vgghp4pks"; repo = "iverilog";
rev = "45fbf558065c0fdac9aa088ecd34e9bf49e81305";
sha256 = "137p7gkmp5kwih93i2a3lcf36a6k38j7fxglvw9y59w0233vj452";
}; };
buildInputs = [ gperf flex bison ]; patchPhase = ''
chmod +x $PWD/autoconf.sh
$PWD/autoconf.sh
'';
buildInputs = [ autoconf gperf flex bison ];
meta = { meta = {
description = "Icarus Verilog compiler"; description = "Icarus Verilog compiler";

6
pkgs/development/compilers/arachne-pnr/default.nix
View file

@ -2,13 +2,13 @@
stdenv.mkDerivation rec { stdenv.mkDerivation rec {
name = "arachne-pnr-${version}"; name = "arachne-pnr-${version}";
version = "2015.12.29"; version = "2016.05.21";
src = fetchFromGitHub { src = fetchFromGitHub {
owner = "cseed"; owner = "cseed";
repo = "arachne-pnr"; repo = "arachne-pnr";
rev = "1a4fdf96a7fd08806c032d41a2443c8e17c72c80"; rev = "6b8336497800782f2f69572d40702b60423ec67f";
sha256 = "1dj7ycffwkmlsh12117fbybkdfnlhxbbxkbfgwfyvcgmg3cacgl1"; sha256 = "11hg17f4lp8azc0ir0i473fz9c0dra82r4fn45cr3amd57v00qbf";
}; };
preBuild = '' preBuild = ''

11
pkgs/development/compilers/yosys/default.nix
View file

@ -2,21 +2,21 @@
stdenv.mkDerivation rec { stdenv.mkDerivation rec {
name = "yosys-${version}"; name = "yosys-${version}";
version = "2015.12.29"; version = "2016.05.21";
srcs = [ srcs = [
(fetchFromGitHub { (fetchFromGitHub {
owner = "cliffordwolf"; owner = "cliffordwolf";
repo = "yosys"; repo = "yosys";
rev = "1d62f8710f04fec405ef79b9e9a4a031afcf7d42"; rev = "8e9e793126a2772eed4b041bc60415943c71d5ee";
sha256 = "0q1dk9in3gmrihb58pjckncx56lj7y4b6y34jgb68f0fh91fdvfx"; sha256 = "1s0x7n7qh2qbfc0d7p4q10fvkr61jdqgyqzijr422rabh9zl4val";
name = "yosys"; name = "yosys";
}) })
(fetchFromBitbucket { (fetchFromBitbucket {
owner = "alanmi"; owner = "alanmi";
repo = "abc"; repo = "abc";
rev = "c3698e053a7a"; rev = "d9559ab";
sha256 = "05p0fvbr7xvb6w3d7j2r6gynr3ljb6r5q6jvn2zs3ysn2b003qwd"; sha256 = "08far669khb65kfpqvjqmqln473j949ak07xibfdjdmiikcy533i";
name = "abc"; name = "abc";
}) })
]; ];
@ -37,7 +37,6 @@ stdenv.mkDerivation rec {
Yosys is a framework for RTL synthesis tools. It currently has Yosys is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains. synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++ adding additional passes as needed by extending the yosys C++

8
pkgs/development/tools/icestorm/default.nix
View file

@ -2,18 +2,18 @@
stdenv.mkDerivation rec { stdenv.mkDerivation rec {
name = "icestorm-${version}"; name = "icestorm-${version}";
version = "2015.12.29"; version = "2016.05.21";
src = fetchFromGitHub { src = fetchFromGitHub {
owner = "cliffordwolf"; owner = "cliffordwolf";
repo = "icestorm"; repo = "icestorm";
rev = "7852514c2cde208da87b62777b2c5e482092f50d"; rev = "fb67695a883b29ca670b43ed2733eca9ca161e4d";
sha256 = "1ya1nk5h28hjdmd8jdrlfiayr2434rnvi133gs1p0ay21qb3iwfz"; sha256 = "0zsjpz49qr09g33nz4nfi1inshg37y5zdxnv6f8gkwq7x948rh3z";
}; };
buildInputs = [ python3 libftdi ]; buildInputs = [ python3 libftdi ];
preBuild = '' preBuild = ''
makeFlags="DESTDIR=$out $makeFlags" makeFlags="PREFIX=$out $makeFlags"
''; '';
meta = { meta = {