Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
285 lines
6.1 KiB
C
285 lines
6.1 KiB
C
/*
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* linux/arch/arm/mach-pxa/generic.c
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* Code common to all PXA machines.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Since this file should be linked before any other machine specific file,
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* the __initcall() here will be executed first. This serves as default
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* initialization stuff for PXA machines which can be overridden later if
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* need be.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/pm.h>
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#include <linux/string.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/gpio.h>
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#include "generic.h"
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/*
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* Get the clock frequency as reflected by CCCR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int get_clk_frequency_khz(int info)
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{
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if (cpu_is_pxa21x() || cpu_is_pxa25x())
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return pxa25x_get_clk_frequency_khz(info);
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else if (cpu_is_pxa27x())
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return pxa27x_get_clk_frequency_khz(info);
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else
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return pxa3xx_get_clk_frequency_khz(info);
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}
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EXPORT_SYMBOL(get_clk_frequency_khz);
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/*
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* Return the current memory clock frequency in units of 10kHz
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*/
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unsigned int get_memclk_frequency_10khz(void)
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{
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if (cpu_is_pxa21x() || cpu_is_pxa25x())
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return pxa25x_get_memclk_frequency_10khz();
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else if (cpu_is_pxa27x())
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return pxa27x_get_memclk_frequency_10khz();
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else
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return pxa3xx_get_memclk_frequency_10khz();
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}
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EXPORT_SYMBOL(get_memclk_frequency_10khz);
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/*
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* Handy function to set GPIO alternate functions
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*/
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int pxa_last_gpio;
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int pxa_gpio_mode(int gpio_mode)
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{
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unsigned long flags;
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int gpio = gpio_mode & GPIO_MD_MASK_NR;
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int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
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int gafr;
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if (gpio > pxa_last_gpio)
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return -EINVAL;
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local_irq_save(flags);
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if (gpio_mode & GPIO_DFLT_LOW)
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GPCR(gpio) = GPIO_bit(gpio);
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else if (gpio_mode & GPIO_DFLT_HIGH)
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GPSR(gpio) = GPIO_bit(gpio);
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if (gpio_mode & GPIO_MD_MASK_DIR)
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GPDR(gpio) |= GPIO_bit(gpio);
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else
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GPDR(gpio) &= ~GPIO_bit(gpio);
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gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
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GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(pxa_gpio_mode);
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int gpio_direction_input(unsigned gpio)
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{
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unsigned long flags;
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u32 mask;
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if (gpio > pxa_last_gpio)
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return -EINVAL;
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mask = GPIO_bit(gpio);
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local_irq_save(flags);
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GPDR(gpio) &= ~mask;
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_input);
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int gpio_direction_output(unsigned gpio, int value)
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{
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unsigned long flags;
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u32 mask;
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if (gpio > pxa_last_gpio)
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return -EINVAL;
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mask = GPIO_bit(gpio);
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local_irq_save(flags);
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if (value)
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GPSR(gpio) = mask;
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else
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GPCR(gpio) = mask;
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GPDR(gpio) |= mask;
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_output);
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/*
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* Return GPIO level
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*/
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int pxa_gpio_get_value(unsigned gpio)
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{
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return __gpio_get_value(gpio);
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}
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EXPORT_SYMBOL(pxa_gpio_get_value);
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/*
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* Set output GPIO level
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*/
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void pxa_gpio_set_value(unsigned gpio, int value)
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{
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__gpio_set_value(gpio, value);
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}
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EXPORT_SYMBOL(pxa_gpio_set_value);
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/*
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* Routine to safely enable or disable a clock in the CKEN
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*/
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void __pxa_set_cken(int clock, int enable)
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{
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unsigned long flags;
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local_irq_save(flags);
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if (enable)
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CKEN |= (1 << clock);
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else
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CKEN &= ~(1 << clock);
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(__pxa_set_cken);
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/*
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* Intel PXA2xx internal register mapping.
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*
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* Note 1: not all PXA2xx variants implement all those addresses.
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*
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* Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
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* and cache flush area.
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*/
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static struct map_desc standard_io_desc[] __initdata = {
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{ /* Devs */
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.virtual = 0xf2000000,
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.pfn = __phys_to_pfn(0x40000000),
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.length = 0x02000000,
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.type = MT_DEVICE
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}, { /* LCD */
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.virtual = 0xf4000000,
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.pfn = __phys_to_pfn(0x44000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* Mem Ctl */
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.virtual = 0xf6000000,
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.pfn = __phys_to_pfn(0x48000000),
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.length = 0x00200000,
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.type = MT_DEVICE
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}, { /* USB host */
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.virtual = 0xf8000000,
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.pfn = __phys_to_pfn(0x4c000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* Camera */
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.virtual = 0xfa000000,
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.pfn = __phys_to_pfn(0x50000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* IMem ctl */
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.virtual = 0xfe000000,
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.pfn = __phys_to_pfn(0x58000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* UNCACHED_PHYS_0 */
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.virtual = 0xff000000,
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.pfn = __phys_to_pfn(0x00000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}
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};
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void __init pxa_map_io(void)
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{
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iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
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get_clk_frequency_khz(1);
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}
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#ifdef CONFIG_PM
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static unsigned long saved_gplr[4];
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static unsigned long saved_gpdr[4];
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static unsigned long saved_grer[4];
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static unsigned long saved_gfer[4];
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static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
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{
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int i, gpio;
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for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
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saved_gplr[i] = GPLR(gpio);
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saved_gpdr[i] = GPDR(gpio);
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saved_grer[i] = GRER(gpio);
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saved_gfer[i] = GFER(gpio);
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/* Clear GPIO transition detect bits */
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GEDR(gpio) = GEDR(gpio);
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}
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return 0;
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}
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static int pxa_gpio_resume(struct sys_device *dev)
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{
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int i, gpio;
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for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
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/* restore level with set/clear */
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GPSR(gpio) = saved_gplr[i];
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GPCR(gpio) = ~saved_gplr[i];
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GRER(gpio) = saved_grer[i];
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GFER(gpio) = saved_gfer[i];
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GPDR(gpio) = saved_gpdr[i];
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}
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return 0;
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}
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#else
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#define pxa_gpio_suspend NULL
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#define pxa_gpio_resume NULL
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#endif
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struct sysdev_class pxa_gpio_sysclass = {
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.name = "gpio",
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.suspend = pxa_gpio_suspend,
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.resume = pxa_gpio_resume,
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};
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static int __init pxa_gpio_init(void)
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{
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return sysdev_class_register(&pxa_gpio_sysclass);
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}
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core_initcall(pxa_gpio_init);
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