c1821c2e97
This provides a noexec protection on s390 hardware. Our hardware does not have any bits left in the pte for a hw noexec bit, so this is a different approach using shadow page tables and a special addressing mode that allows separate address spaces for code and data. As a special feature of our "secondary-space" addressing mode, separate page tables can be specified for the translation of data addresses (storage operands) and instruction addresses. The shadow page table is used for the instruction addresses and the standard page table for the data addresses. The shadow page table is linked to the standard page table by a pointer in page->lru.next of the struct page corresponding to the page that contains the standard page table (since page->private is not really private with the pte_lock and the page table pages are not in the LRU list). Depending on the software bits of a pte, it is either inserted into both page tables or just into the standard (data) page table. Pages of a vma that does not have the VM_EXEC bit set get mapped only in the data address space. Any try to execute code on such a page will cause a page translation exception. The standard reaction to this is a SIGSEGV with two exceptions: the two system call opcodes 0x0a77 (sys_sigreturn) and 0x0aad (sys_rt_sigreturn) are allowed. They are stored by the kernel to the signal stack frame. Unfortunately, the signal return mechanism cannot be modified to use an SA_RESTORER because the exception unwinding code depends on the system call opcode stored behind the signal stack frame. This feature requires that user space is executed in secondary-space mode and the kernel in home-space mode, which means that the addressing modes need to be switched and that the noexec protection only works for user space. After switching the addressing modes, we cannot use the mvcp/mvcs instructions anymore to copy between kernel and user space. A new mvcos instruction has been added to the z9 EC/BC hardware which allows to copy between arbitrary address spaces, but on older hardware the page tables need to be walked manually. Signed-off-by: Gerald Schaefer <geraldsc@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
/*
|
|
* include/asm-s390/smp.h
|
|
*
|
|
* S390 version
|
|
* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
|
|
* Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
|
|
* Martin Schwidefsky (schwidefsky@de.ibm.com)
|
|
* Heiko Carstens (heiko.carstens@de.ibm.com)
|
|
*/
|
|
#ifndef __ASM_SMP_H
|
|
#define __ASM_SMP_H
|
|
|
|
#include <linux/threads.h>
|
|
#include <linux/cpumask.h>
|
|
#include <linux/bitops.h>
|
|
|
|
#if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
|
|
|
|
#include <asm/lowcore.h>
|
|
#include <asm/sigp.h>
|
|
#include <asm/ptrace.h>
|
|
|
|
/*
|
|
s390 specific smp.c headers
|
|
*/
|
|
typedef struct
|
|
{
|
|
int intresting;
|
|
sigp_ccode ccode;
|
|
__u32 status;
|
|
__u16 cpu;
|
|
} sigp_info;
|
|
|
|
extern void machine_restart_smp(char *);
|
|
extern void machine_halt_smp(void);
|
|
extern void machine_power_off_smp(void);
|
|
|
|
extern void smp_setup_cpu_possible_map(void);
|
|
extern int smp_call_function_on(void (*func) (void *info), void *info,
|
|
int nonatomic, int wait, int cpu);
|
|
#define NO_PROC_ID 0xFF /* No processor magic marker */
|
|
|
|
/*
|
|
* This magic constant controls our willingness to transfer
|
|
* a process across CPUs. Such a transfer incurs misses on the L1
|
|
* cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
|
|
* gut feeling is this will vary by board in value. For a board
|
|
* with separate L2 cache it probably depends also on the RSS, and
|
|
* for a board with shared L2 cache it ought to decay fast as other
|
|
* processes are run.
|
|
*/
|
|
|
|
#define PROC_CHANGE_PENALTY 20 /* Schedule penalty */
|
|
|
|
#define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr)
|
|
|
|
extern int smp_get_cpu(cpumask_t cpu_map);
|
|
extern void smp_put_cpu(int cpu);
|
|
|
|
static inline __u16 hard_smp_processor_id(void)
|
|
{
|
|
__u16 cpu_address;
|
|
|
|
asm volatile("stap %0" : "=m" (cpu_address));
|
|
return cpu_address;
|
|
}
|
|
|
|
/*
|
|
* returns 1 if cpu is in stopped/check stopped state or not operational
|
|
* returns 0 otherwise
|
|
*/
|
|
static inline int
|
|
smp_cpu_not_running(int cpu)
|
|
{
|
|
__u32 status;
|
|
|
|
switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
|
|
case sigp_order_code_accepted:
|
|
case sigp_status_stored:
|
|
/* Check for stopped and check stop state */
|
|
if (status & 0x50)
|
|
return 1;
|
|
break;
|
|
case sigp_not_operational:
|
|
return 1;
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#define cpu_logical_map(cpu) (cpu)
|
|
|
|
extern int __cpu_disable (void);
|
|
extern void __cpu_die (unsigned int cpu);
|
|
extern void cpu_die (void) __attribute__ ((noreturn));
|
|
extern int __cpu_up (unsigned int cpu);
|
|
|
|
#endif
|
|
|
|
#ifndef CONFIG_SMP
|
|
static inline int
|
|
smp_call_function_on(void (*func) (void *info), void *info,
|
|
int nonatomic, int wait, int cpu)
|
|
{
|
|
func(info);
|
|
return 0;
|
|
}
|
|
|
|
static inline void smp_send_stop(void)
|
|
{
|
|
/* Disable all interrupts/machine checks */
|
|
__load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK);
|
|
}
|
|
|
|
#define smp_cpu_not_running(cpu) 1
|
|
#define smp_get_cpu(cpu) ({ 0; })
|
|
#define smp_put_cpu(cpu) ({ 0; })
|
|
#define smp_setup_cpu_possible_map() do { } while (0)
|
|
#endif
|
|
|
|
#endif
|