938fa349fb
Replace the ugly hack that inserts legacy irq controller calls into the irq call paths by reading and replacing the gic irq chip with the new gic arch extensions. Signed-off-by: Colin Cross <ccross@android.com>
138 lines
3.2 KiB
C
138 lines
3.2 KiB
C
/*
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* Copyright (C) 2011 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* Copyright (C) 2010, NVIDIA Corporation
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/gic.h>
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#include <mach/iomap.h>
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#include <mach/legacy_irq.h>
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#include <mach/suspend.h>
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#include "board.h"
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#define PMC_CTRL 0x0
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#define PMC_CTRL_LATCH_WAKEUPS (1 << 5)
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#define PMC_WAKE_MASK 0xc
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#define PMC_WAKE_LEVEL 0x10
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#define PMC_WAKE_STATUS 0x14
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#define PMC_SW_WAKE_STATUS 0x18
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#define PMC_DPD_SAMPLE 0x20
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static u32 tegra_lp0_wake_enb;
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static u32 tegra_lp0_wake_level;
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static u32 tegra_lp0_wake_level_any;
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/* ensures that sufficient time is passed for a register write to
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* serialize into the 32KHz domain */
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static void pmc_32kwritel(u32 val, unsigned long offs)
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{
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writel(val, pmc + offs);
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udelay(130);
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}
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int tegra_set_lp1_wake(int irq, int enable)
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{
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return tegra_legacy_irq_set_wake(irq, enable);
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}
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void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
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{
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u32 temp;
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u32 status;
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u32 lvl;
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wake_level &= wake_enb;
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wake_any &= wake_enb;
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wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
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wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
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wake_enb |= tegra_lp0_wake_enb;
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pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
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temp = readl(pmc + PMC_CTRL);
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temp |= PMC_CTRL_LATCH_WAKEUPS;
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pmc_32kwritel(temp, PMC_CTRL);
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temp &= ~PMC_CTRL_LATCH_WAKEUPS;
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pmc_32kwritel(temp, PMC_CTRL);
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status = readl(pmc + PMC_SW_WAKE_STATUS);
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lvl = readl(pmc + PMC_WAKE_LEVEL);
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/* flip the wakeup trigger for any-edge triggered pads
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* which are currently asserting as wakeups */
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lvl ^= status;
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lvl &= wake_any;
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wake_level |= lvl;
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writel(wake_level, pmc + PMC_WAKE_LEVEL);
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/* Enable DPD sample to trigger sampling pads data and direction
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* in which pad will be driven during lp0 mode*/
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writel(0x1, pmc + PMC_DPD_SAMPLE);
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writel(wake_enb, pmc + PMC_WAKE_MASK);
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}
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static void tegra_mask(struct irq_data *d)
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{
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if (d->irq >= 32)
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tegra_legacy_mask_irq(d->irq);
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}
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static void tegra_unmask(struct irq_data *d)
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{
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if (d->irq >= 32)
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tegra_legacy_unmask_irq(d->irq);
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}
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static void tegra_ack(struct irq_data *d)
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{
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if (d->irq >= 32)
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tegra_legacy_force_irq_clr(d->irq);
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}
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static int tegra_retrigger(struct irq_data *d)
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{
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if (d->irq < 32)
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return 0;
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tegra_legacy_force_irq_set(d->irq);
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return 1;
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}
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void __init tegra_init_irq(void)
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{
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tegra_init_legacy_irq();
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gic_arch_extn.irq_ack = tegra_ack;
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gic_arch_extn.irq_mask = tegra_mask;
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gic_arch_extn.irq_unmask = tegra_unmask;
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gic_arch_extn.irq_retrigger = tegra_retrigger;
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gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
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IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
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}
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