583ecab9e3
The l2x0 level 2 cache initialization used a static map to get at the l2x0 registers. Get rid of this by getting the register range from the device tree and just remap it for the short time we need it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2011
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "db8500-regs.h"
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#include "id.h"
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static int __init ux500_l2x0_unlock(void)
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{
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int i;
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struct device_node *np;
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void __iomem *l2x0_base;
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np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
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l2x0_base = of_iomap(np, 0);
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of_node_put(np);
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if (!l2x0_base)
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return -ENODEV;
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/*
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* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
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* apparently locks both caches before jumping to the kernel. The
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* l2x0 core will not touch the unlock registers if the l2x0 is
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* already enabled, so we do it right here instead. The PL310 has
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* 8 sets of registers, one per possible CPU.
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*/
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for (i = 0; i < 8; i++) {
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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}
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iounmap(l2x0_base);
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return 0;
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}
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static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
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{
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/*
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* We can't write to secure registers as we are in non-secure
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* mode, until we have some SMI service available.
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*/
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}
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static int __init ux500_l2x0_init(void)
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{
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/* Multiplatform guard */
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if (!((cpu_is_u8500_family() || cpu_is_ux540_family())))
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return -ENODEV;
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/* Unlock before init */
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ux500_l2x0_unlock();
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outer_cache.write_sec = ux500_l2c310_write_sec;
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l2x0_of_init(0, ~0);
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return 0;
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}
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early_initcall(ux500_l2x0_init);
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