Second set of OMAP PRCM cleanups for 3.8. These patches remove the use of omap_prcm_get_reset_sources() from the OMAP watchdog driver, and remove mach-omap2/prcm.c and plat-omap/include/plat/prcm.h. Basic test logs for this branch on top of Tony's cleanup-prcm branch at commit7fc54fd308
are here: http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121108151646/ However, cleanup-prcm at7fc54fd3
does not include some fixes that are needed for a successful test. With several reverts, fixes, and workarounds applied, the following test logs were obtained: http://www.pwsan.com/omap/testlogs/TEST_prcm_cleanup_b_3.8/20121108151930/ which indicate that the series tests cleanly. This second pull request updates one of the patches which broke with rmk's allnoconfigs, and also updates the tag description to indicate that7fc54fd3
is building cleanly here. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQoY0GAAoJEBvUPslcq6Vza0MQAI0idVoOclIHCC63tpc58YWA BpD5OLg4yRu0RUFS1CI/Fq5d+9PfYUspgaWja3TTgUy0EHRDVUUFRaxJdpWdl2NF gX7BCuhnQenznTbCE80nEmxvsh7U/dfvs+JYUK2PriypU61f1+TnSu9ZxTRvDJOx vbo1cfsioVcLfnBPSDSQVJ1fufbafklpeQkDNeRI8UDsCVeXwnxhNsXB3utoJMf0 5gaDaCdRBoimkLnAaLi41OnHYC7IbNCnl/VX0i/xffROsINfL7LDkBPfUOnR5vle jTCV49UEB/P5ekk2cvKKj8IOQZdimiCppWMLit6DObX7LbltTKuXx6T0PclgxQ14 hhav5O+f8NYA4yDAY/xxPlTvShMr8rQcYV6pg1G1OgD+dcq7cbbWNJAvbUJ03hH8 dqZ+ypLYkazb3Mm5XtpFr47gkoaFnCQbgZLXpjJ8+L01aGNrF2L6aE789So1N81+ X1s0ENjRxzDLNcqwxqhcoph0YQe7GlyiviYb7ev25MTSC3/TjrupTViZbKocZmLt Ad9m4SOktbHthAw0jdA48vOmPiSvmYzFiqzMhz/ryeNbyyV6rRxe5w4JUjPzHPxc U7NraSGIAzpqM3EKEp7Rb0yOfh6sGzML/FH9bS25+Rv37yKW0huc6ENIRgatZpY2 blLzsxaKfQgLeqKT82mj =tS2z -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.8/cleanup-prcm-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup From Tony Lindgren <tony@atomide.com>: More PRCM cleanups via Paul Walmsley <paul@pwsan.com>: Second set of OMAP PRCM cleanups for 3.8. These patches remove the use of omap_prcm_get_reset_sources() from the OMAP watchdog driver, and remove mach-omap2/prcm.c and plat-omap/include/plat/prcm.h. Basic test logs for this branch on top of Tony's cleanup-prcm branch at commit7fc54fd308
are here: http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121108151646/ However, cleanup-prcm at7fc54fd3
does not include some fixes that are needed for a successful test. With several reverts, fixes, and workarounds applied, the following test logs were obtained: http://www.pwsan.com/omap/testlogs/TEST_prcm_cleanup_b_3.8/20121108151930/ which indicate that the series tests cleanly. This second pull request updates one of the patches which broke with rmk's allnoconfigs, and also updates the tag description to indicate that7fc54fd3
is building cleanly here. * tag 'omap-for-v3.8/cleanup-prcm-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (27 commits) ARM: OMAP2: Fix compillation error in cm_common ARM: OMAP2+: PRCM: remove obsolete prcm.[ch] ARM: OMAP2+: hwmod: call to _omap4_disable_module() should use the SoC-specific call ARM: OMAP2+: PRCM: consolidate PRCM-related timeout macros ARM: OMAP2+: PRCM: split and relocate the PRM/CM globals setup ARM: OMAP2+: PRCM: remove omap2_cm_wait_idlest() ARM: OMAP2+: CM/clock: convert _omap2_module_wait_ready() to use SoC-independent CM functions ARM: OMAP2xxx: APLL/CM: convert to use omap2_cm_wait_module_ready() ARM: OMAP2+: board files: use SoC-specific system restart functions ARM: OMAP2+: PRCM: create SoC-specific chip restart functions ARM: OMAP2xxx: clock: move virt_prcm_set code into clkt2xxx_virt_prcm_set.c ARM: OMAP2xxx: clock: remove global 'dclk' variable ARM: OMAP2/3: PRM: add SoC reset functions (using the CORE DPLL method) ARM: OMAP2+: common: remove mach-omap2/common.c globals and map_common_io code ARM: OMAP2+: PRCM: remove omap_prcm_get_reset_sources() watchdog: OMAP: use standard GETBOOTSTATUS interface; use platform_data fn ptr ARM: OMAP2+: WDT: move init; add read_reset_sources pdata function pointer ARM: OMAP1: CGRM: fix omap1_get_reset_sources() return type ARM: OMAP2+: PRM: create PRM reset source API for the watchdog timer driver ARM: OMAP1: create read_reset_sources() function (for initial use by watchdog) ... Conflicts: arch/arm/mach-omap2/cm33xx.c arch/arm/mach-omap2/io.c arch/arm/mach-omap2/prm_common.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
219 lines
5.9 KiB
C
219 lines
5.9 KiB
C
/*
|
|
* OMAP2xxx DVFS virtual clock functions
|
|
*
|
|
* Copyright (C) 2005-2008, 2012 Texas Instruments, Inc.
|
|
* Copyright (C) 2004-2010 Nokia Corporation
|
|
*
|
|
* Contacts:
|
|
* Richard Woodruff <r-woodruff2@ti.com>
|
|
* Paul Walmsley
|
|
*
|
|
* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
|
|
* Gordon McNutt and RidgeRun, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* XXX Some of this code should be replaceable by the upcoming OPP layer
|
|
* code. However, some notion of "rate set" is probably still necessary
|
|
* for OMAP2xxx at least. Rate sets should be generalized so they can be
|
|
* used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff
|
|
* has in the past expressed a preference to use rate sets for OPP changes,
|
|
* rather than dynamically recalculating the clock tree, so if someone wants
|
|
* this badly enough to write the code to handle it, we should support it
|
|
* as an option.
|
|
*/
|
|
#undef DEBUG
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/clk.h>
|
|
#include <linux/io.h>
|
|
#include <linux/cpufreq.h>
|
|
#include <linux/slab.h>
|
|
|
|
#include "soc.h"
|
|
#include "clock.h"
|
|
#include "clock2xxx.h"
|
|
#include "opp2xxx.h"
|
|
#include "cm2xxx.h"
|
|
#include "cm-regbits-24xx.h"
|
|
#include "sdrc.h"
|
|
#include "sram.h"
|
|
|
|
const struct prcm_config *curr_prcm_set;
|
|
const struct prcm_config *rate_table;
|
|
|
|
/*
|
|
* sys_ck_rate: the rate of the external high-frequency clock
|
|
* oscillator on the board. Set by the SoC-specific clock init code.
|
|
* Once set during a boot, will not change.
|
|
*/
|
|
static unsigned long sys_ck_rate;
|
|
|
|
/**
|
|
* omap2_table_mpu_recalc - just return the MPU speed
|
|
* @clk: virt_prcm_set struct clk
|
|
*
|
|
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
|
|
*/
|
|
unsigned long omap2_table_mpu_recalc(struct clk *clk)
|
|
{
|
|
return curr_prcm_set->mpu_speed;
|
|
}
|
|
|
|
/*
|
|
* Look for a rate equal or less than the target rate given a configuration set.
|
|
*
|
|
* What's not entirely clear is "which" field represents the key field.
|
|
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
|
|
* just uses the ARM rates.
|
|
*/
|
|
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
const struct prcm_config *ptr;
|
|
long highest_rate;
|
|
|
|
highest_rate = -EINVAL;
|
|
|
|
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
|
|
if (!(ptr->flags & cpu_mask))
|
|
continue;
|
|
if (ptr->xtal_speed != sys_ck_rate)
|
|
continue;
|
|
|
|
highest_rate = ptr->mpu_speed;
|
|
|
|
/* Can check only after xtal frequency check */
|
|
if (ptr->mpu_speed <= rate)
|
|
break;
|
|
}
|
|
return highest_rate;
|
|
}
|
|
|
|
/* Sets basic clocks based on the specified rate */
|
|
int omap2_select_table_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
u32 cur_rate, done_rate, bypass = 0, tmp;
|
|
const struct prcm_config *prcm;
|
|
unsigned long found_speed = 0;
|
|
unsigned long flags;
|
|
|
|
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
|
if (!(prcm->flags & cpu_mask))
|
|
continue;
|
|
|
|
if (prcm->xtal_speed != sys_ck_rate)
|
|
continue;
|
|
|
|
if (prcm->mpu_speed <= rate) {
|
|
found_speed = prcm->mpu_speed;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!found_speed) {
|
|
printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
|
|
rate / 1000000);
|
|
return -EINVAL;
|
|
}
|
|
|
|
curr_prcm_set = prcm;
|
|
cur_rate = omap2xxx_clk_get_core_rate();
|
|
|
|
if (prcm->dpll_speed == cur_rate / 2) {
|
|
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
|
|
} else if (prcm->dpll_speed == cur_rate * 2) {
|
|
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
|
} else if (prcm->dpll_speed != cur_rate) {
|
|
local_irq_save(flags);
|
|
|
|
if (prcm->dpll_speed == prcm->xtal_speed)
|
|
bypass = 1;
|
|
|
|
if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
|
|
CORE_CLK_SRC_DPLL_X2)
|
|
done_rate = CORE_CLK_SRC_DPLL_X2;
|
|
else
|
|
done_rate = CORE_CLK_SRC_DPLL;
|
|
|
|
/* MPU divider */
|
|
omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
|
|
|
|
/* dsp + iva1 div(2420), iva2.1(2430) */
|
|
omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
|
|
OMAP24XX_DSP_MOD, CM_CLKSEL);
|
|
|
|
omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
|
|
|
|
/* Major subsystem dividers */
|
|
tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
|
|
omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
|
|
CM_CLKSEL1);
|
|
|
|
if (cpu_is_omap2430())
|
|
omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
|
|
OMAP2430_MDM_MOD, CM_CLKSEL);
|
|
|
|
/* x2 to enter omap2xxx_sdrc_init_params() */
|
|
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
|
|
|
omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
|
|
bypass);
|
|
|
|
omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
|
|
omap2xxx_sdrc_reprogram(done_rate, 0);
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* omap2xxx_clkt_vps_check_bootloader_rate - determine which of the rate
|
|
* table sets matches the current CORE DPLL hardware rate
|
|
*
|
|
* Check the MPU rate set by bootloader. Sets the 'curr_prcm_set'
|
|
* global to point to the active rate set when found; otherwise, sets
|
|
* it to NULL. No return value;
|
|
*/
|
|
void omap2xxx_clkt_vps_check_bootloader_rates(void)
|
|
{
|
|
const struct prcm_config *prcm = NULL;
|
|
unsigned long rate;
|
|
|
|
rate = omap2xxx_clk_get_core_rate();
|
|
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
|
if (!(prcm->flags & cpu_mask))
|
|
continue;
|
|
if (prcm->xtal_speed != sys_ck_rate)
|
|
continue;
|
|
if (prcm->dpll_speed <= rate)
|
|
break;
|
|
}
|
|
curr_prcm_set = prcm;
|
|
}
|
|
|
|
/**
|
|
* omap2xxx_clkt_vps_late_init - store a copy of the sys_ck rate
|
|
*
|
|
* Store a copy of the sys_ck rate for later use by the OMAP2xxx DVFS
|
|
* code. (The sys_ck rate does not -- or rather, must not -- change
|
|
* during kernel runtime.) Must be called after we have a valid
|
|
* sys_ck rate, but before the virt_prcm_set clock rate is
|
|
* recalculated. No return value.
|
|
*/
|
|
void omap2xxx_clkt_vps_late_init(void)
|
|
{
|
|
struct clk *c;
|
|
|
|
c = clk_get(NULL, "sys_ck");
|
|
if (IS_ERR(c)) {
|
|
WARN(1, "could not locate sys_ck\n");
|
|
} else {
|
|
sys_ck_rate = clk_get_rate(c);
|
|
clk_put(c);
|
|
}
|
|
}
|