1165 lines
27 KiB
C
1165 lines
27 KiB
C
/*
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* linux/arch/arm/kernel/setup.c
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*
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* Copyright (C) 1995-2001 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/utsname.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/screen_info.h>
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#include <linux/of_iommu.h>
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#include <linux/of_platform.h>
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#include <linux/init.h>
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#include <linux/kexec.h>
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#include <linux/of_fdt.h>
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/proc_fs.h>
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#include <linux/memblock.h>
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#include <linux/bug.h>
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#include <linux/compiler.h>
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#include <linux/sort.h>
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#include <linux/psci.h>
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#include <asm/unified.h>
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#include <asm/cp15.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/elf.h>
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#include <asm/fixmap.h>
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#include <asm/procinfo.h>
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#include <asm/psci.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/smp_plat.h>
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#include <asm/mach-types.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/tlbflush.h>
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#include <asm/xen/hypervisor.h>
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#include <asm/prom.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/system_info.h>
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#include <asm/system_misc.h>
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#include <asm/traps.h>
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#include <asm/unwind.h>
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#include <asm/memblock.h>
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#include <asm/virt.h>
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#include "atags.h"
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#if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
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char fpe_type[8];
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static int __init fpe_setup(char *line)
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{
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memcpy(fpe_type, line, 8);
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return 1;
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}
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__setup("fpe=", fpe_setup);
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#endif
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extern void init_default_cache_policy(unsigned long);
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extern void paging_init(const struct machine_desc *desc);
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extern void early_paging_init(const struct machine_desc *);
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extern void sanity_check_meminfo(void);
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extern enum reboot_mode reboot_mode;
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extern void setup_dma_zone(const struct machine_desc *desc);
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unsigned int processor_id;
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EXPORT_SYMBOL(processor_id);
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unsigned int __machine_arch_type __read_mostly;
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EXPORT_SYMBOL(__machine_arch_type);
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unsigned int cacheid __read_mostly;
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EXPORT_SYMBOL(cacheid);
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unsigned int __atags_pointer __initdata;
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unsigned int system_rev;
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EXPORT_SYMBOL(system_rev);
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const char *system_serial;
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EXPORT_SYMBOL(system_serial);
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unsigned int system_serial_low;
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EXPORT_SYMBOL(system_serial_low);
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unsigned int system_serial_high;
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EXPORT_SYMBOL(system_serial_high);
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unsigned int elf_hwcap __read_mostly;
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EXPORT_SYMBOL(elf_hwcap);
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unsigned int elf_hwcap2 __read_mostly;
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EXPORT_SYMBOL(elf_hwcap2);
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#ifdef MULTI_CPU
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struct processor processor __read_mostly;
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#endif
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#ifdef MULTI_TLB
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struct cpu_tlb_fns cpu_tlb __read_mostly;
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#endif
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#ifdef MULTI_USER
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struct cpu_user_fns cpu_user __read_mostly;
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#endif
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#ifdef MULTI_CACHE
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struct cpu_cache_fns cpu_cache __read_mostly;
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#endif
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#ifdef CONFIG_OUTER_CACHE
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struct outer_cache_fns outer_cache __read_mostly;
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EXPORT_SYMBOL(outer_cache);
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#endif
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/*
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* Cached cpu_architecture() result for use by assembler code.
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* C code should use the cpu_architecture() function instead of accessing this
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* variable directly.
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*/
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int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
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struct stack {
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u32 irq[3];
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u32 abt[3];
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u32 und[3];
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u32 fiq[3];
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} ____cacheline_aligned;
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#ifndef CONFIG_CPU_V7M
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static struct stack stacks[NR_CPUS];
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#endif
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char elf_platform[ELF_PLATFORM_SIZE];
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EXPORT_SYMBOL(elf_platform);
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static const char *cpu_name;
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static const char *machine_name;
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static char __initdata cmd_line[COMMAND_LINE_SIZE];
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const struct machine_desc *machine_desc __initdata;
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static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
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#define ENDIANNESS ((char)endian_test.l)
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DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
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/*
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* Standard memory resources
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*/
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static struct resource mem_res[] = {
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{
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.name = "Video RAM",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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},
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{
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.name = "Kernel code",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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},
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{
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.name = "Kernel data",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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}
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};
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#define video_ram mem_res[0]
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#define kernel_code mem_res[1]
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#define kernel_data mem_res[2]
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static struct resource io_res[] = {
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{
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.name = "reserved",
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.start = 0x3bc,
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.end = 0x3be,
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.flags = IORESOURCE_IO | IORESOURCE_BUSY
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},
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{
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.name = "reserved",
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.start = 0x378,
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.end = 0x37f,
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.flags = IORESOURCE_IO | IORESOURCE_BUSY
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},
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{
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.name = "reserved",
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.start = 0x278,
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.end = 0x27f,
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.flags = IORESOURCE_IO | IORESOURCE_BUSY
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}
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};
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#define lp0 io_res[0]
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#define lp1 io_res[1]
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#define lp2 io_res[2]
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static const char *proc_arch[] = {
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"undefined/unknown",
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"3",
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"4",
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"4T",
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"5",
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"5T",
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"5TE",
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"5TEJ",
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"6TEJ",
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"7",
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"7M",
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"?(12)",
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"?(13)",
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"?(14)",
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"?(15)",
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"?(16)",
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"?(17)",
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};
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#ifdef CONFIG_CPU_V7M
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static int __get_cpu_architecture(void)
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{
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return CPU_ARCH_ARMv7M;
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}
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#else
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static int __get_cpu_architecture(void)
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{
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int cpu_arch;
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if ((read_cpuid_id() & 0x0008f000) == 0) {
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cpu_arch = CPU_ARCH_UNKNOWN;
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} else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
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cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
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} else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
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cpu_arch = (read_cpuid_id() >> 16) & 7;
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if (cpu_arch)
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cpu_arch += CPU_ARCH_ARMv3;
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} else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
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/* Revised CPUID format. Read the Memory Model Feature
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* Register 0 and check for VMSAv7 or PMSAv7 */
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unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
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if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
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(mmfr0 & 0x000000f0) >= 0x00000030)
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cpu_arch = CPU_ARCH_ARMv7;
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else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
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(mmfr0 & 0x000000f0) == 0x00000020)
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cpu_arch = CPU_ARCH_ARMv6;
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else
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cpu_arch = CPU_ARCH_UNKNOWN;
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} else
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cpu_arch = CPU_ARCH_UNKNOWN;
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return cpu_arch;
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}
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#endif
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int __pure cpu_architecture(void)
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{
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BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
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return __cpu_architecture;
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}
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static int cpu_has_aliasing_icache(unsigned int arch)
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{
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int aliasing_icache;
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unsigned int id_reg, num_sets, line_size;
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/* PIPT caches never alias. */
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if (icache_is_pipt())
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return 0;
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/* arch specifies the register format */
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switch (arch) {
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case CPU_ARCH_ARMv7:
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asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
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: /* No output operands */
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: "r" (1));
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isb();
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asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
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: "=r" (id_reg));
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line_size = 4 << ((id_reg & 0x7) + 2);
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num_sets = ((id_reg >> 13) & 0x7fff) + 1;
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aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
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break;
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case CPU_ARCH_ARMv6:
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aliasing_icache = read_cpuid_cachetype() & (1 << 11);
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break;
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default:
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/* I-cache aliases will be handled by D-cache aliasing code */
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aliasing_icache = 0;
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}
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return aliasing_icache;
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}
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static void __init cacheid_init(void)
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{
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unsigned int arch = cpu_architecture();
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if (arch == CPU_ARCH_ARMv7M) {
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cacheid = 0;
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} else if (arch >= CPU_ARCH_ARMv6) {
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unsigned int cachetype = read_cpuid_cachetype();
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if ((cachetype & (7 << 29)) == 4 << 29) {
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/* ARMv7 register format */
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arch = CPU_ARCH_ARMv7;
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cacheid = CACHEID_VIPT_NONALIASING;
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switch (cachetype & (3 << 14)) {
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case (1 << 14):
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cacheid |= CACHEID_ASID_TAGGED;
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break;
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case (3 << 14):
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cacheid |= CACHEID_PIPT;
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break;
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}
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} else {
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arch = CPU_ARCH_ARMv6;
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if (cachetype & (1 << 23))
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cacheid = CACHEID_VIPT_ALIASING;
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else
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cacheid = CACHEID_VIPT_NONALIASING;
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}
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if (cpu_has_aliasing_icache(arch))
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cacheid |= CACHEID_VIPT_I_ALIASING;
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} else {
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cacheid = CACHEID_VIVT;
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}
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pr_info("CPU: %s data cache, %s instruction cache\n",
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cache_is_vivt() ? "VIVT" :
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cache_is_vipt_aliasing() ? "VIPT aliasing" :
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cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
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cache_is_vivt() ? "VIVT" :
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icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
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icache_is_vipt_aliasing() ? "VIPT aliasing" :
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icache_is_pipt() ? "PIPT" :
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cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
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}
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/*
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* These functions re-use the assembly code in head.S, which
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* already provide the required functionality.
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*/
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extern struct proc_info_list *lookup_processor_type(unsigned int);
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void __init early_print(const char *str, ...)
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{
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extern void printascii(const char *);
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char buf[256];
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va_list ap;
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va_start(ap, str);
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vsnprintf(buf, sizeof(buf), str, ap);
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va_end(ap);
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#ifdef CONFIG_DEBUG_LL
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printascii(buf);
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#endif
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printk("%s", buf);
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}
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static void __init cpuid_init_hwcaps(void)
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{
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int block;
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u32 isar5;
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if (cpu_architecture() < CPU_ARCH_ARMv7)
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return;
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block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
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if (block >= 2)
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elf_hwcap |= HWCAP_IDIVA;
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if (block >= 1)
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elf_hwcap |= HWCAP_IDIVT;
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/* LPAE implies atomic ldrd/strd instructions */
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block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
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if (block >= 5)
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elf_hwcap |= HWCAP_LPAE;
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/* check for supported v8 Crypto instructions */
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isar5 = read_cpuid_ext(CPUID_EXT_ISAR5);
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block = cpuid_feature_extract_field(isar5, 4);
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if (block >= 2)
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elf_hwcap2 |= HWCAP2_PMULL;
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if (block >= 1)
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elf_hwcap2 |= HWCAP2_AES;
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block = cpuid_feature_extract_field(isar5, 8);
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if (block >= 1)
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elf_hwcap2 |= HWCAP2_SHA1;
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block = cpuid_feature_extract_field(isar5, 12);
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if (block >= 1)
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elf_hwcap2 |= HWCAP2_SHA2;
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block = cpuid_feature_extract_field(isar5, 16);
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if (block >= 1)
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elf_hwcap2 |= HWCAP2_CRC32;
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}
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static void __init elf_hwcap_fixup(void)
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{
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unsigned id = read_cpuid_id();
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/*
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* HWCAP_TLS is available only on 1136 r1p0 and later,
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* see also kuser_get_tls_init.
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*/
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if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
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((id >> 20) & 3) == 0) {
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elf_hwcap &= ~HWCAP_TLS;
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return;
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}
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/* Verify if CPUID scheme is implemented */
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if ((id & 0x000f0000) != 0x000f0000)
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return;
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/*
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* If the CPU supports LDREX/STREX and LDREXB/STREXB,
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* avoid advertising SWP; it may not be atomic with
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* multiprocessing cores.
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*/
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if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
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(cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
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cpuid_feature_extract(CPUID_EXT_ISAR3, 20) >= 3))
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elf_hwcap &= ~HWCAP_SWP;
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}
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/*
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* cpu_init - initialise one CPU.
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*
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* cpu_init sets up the per-CPU stacks.
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*/
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void notrace cpu_init(void)
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{
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#ifndef CONFIG_CPU_V7M
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unsigned int cpu = smp_processor_id();
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struct stack *stk = &stacks[cpu];
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if (cpu >= NR_CPUS) {
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pr_crit("CPU%u: bad primary CPU number\n", cpu);
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BUG();
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}
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/*
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* This only works on resume and secondary cores. For booting on the
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* boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
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*/
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set_my_cpu_offset(per_cpu_offset(cpu));
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cpu_proc_init();
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/*
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* Define the placement constraint for the inline asm directive below.
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* In Thumb-2, msr with an immediate value is not allowed.
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*/
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#ifdef CONFIG_THUMB2_KERNEL
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#define PLC "r"
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#else
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#define PLC "I"
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#endif
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/*
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* setup stacks for re-entrant exception handlers
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*/
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__asm__ (
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"msr cpsr_c, %1\n\t"
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"add r14, %0, %2\n\t"
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"mov sp, r14\n\t"
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"msr cpsr_c, %3\n\t"
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"add r14, %0, %4\n\t"
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"mov sp, r14\n\t"
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"msr cpsr_c, %5\n\t"
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"add r14, %0, %6\n\t"
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"mov sp, r14\n\t"
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"msr cpsr_c, %7\n\t"
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"add r14, %0, %8\n\t"
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"mov sp, r14\n\t"
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"msr cpsr_c, %9"
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:
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: "r" (stk),
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PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
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"I" (offsetof(struct stack, irq[0])),
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PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
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"I" (offsetof(struct stack, abt[0])),
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PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
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"I" (offsetof(struct stack, und[0])),
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PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
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"I" (offsetof(struct stack, fiq[0])),
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PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
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: "r14");
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#endif
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}
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u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
|
|
|
|
void __init smp_setup_processor_id(void)
|
|
{
|
|
int i;
|
|
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
|
|
u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
|
|
|
cpu_logical_map(0) = cpu;
|
|
for (i = 1; i < nr_cpu_ids; ++i)
|
|
cpu_logical_map(i) = i == cpu ? 0 : i;
|
|
|
|
/*
|
|
* clear __my_cpu_offset on boot CPU to avoid hang caused by
|
|
* using percpu variable early, for example, lockdep will
|
|
* access percpu variable inside lock_release
|
|
*/
|
|
set_my_cpu_offset(0);
|
|
|
|
pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
|
|
}
|
|
|
|
struct mpidr_hash mpidr_hash;
|
|
#ifdef CONFIG_SMP
|
|
/**
|
|
* smp_build_mpidr_hash - Pre-compute shifts required at each affinity
|
|
* level in order to build a linear index from an
|
|
* MPIDR value. Resulting algorithm is a collision
|
|
* free hash carried out through shifting and ORing
|
|
*/
|
|
static void __init smp_build_mpidr_hash(void)
|
|
{
|
|
u32 i, affinity;
|
|
u32 fs[3], bits[3], ls, mask = 0;
|
|
/*
|
|
* Pre-scan the list of MPIDRS and filter out bits that do
|
|
* not contribute to affinity levels, ie they never toggle.
|
|
*/
|
|
for_each_possible_cpu(i)
|
|
mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
|
|
pr_debug("mask of set bits 0x%x\n", mask);
|
|
/*
|
|
* Find and stash the last and first bit set at all affinity levels to
|
|
* check how many bits are required to represent them.
|
|
*/
|
|
for (i = 0; i < 3; i++) {
|
|
affinity = MPIDR_AFFINITY_LEVEL(mask, i);
|
|
/*
|
|
* Find the MSB bit and LSB bits position
|
|
* to determine how many bits are required
|
|
* to express the affinity level.
|
|
*/
|
|
ls = fls(affinity);
|
|
fs[i] = affinity ? ffs(affinity) - 1 : 0;
|
|
bits[i] = ls - fs[i];
|
|
}
|
|
/*
|
|
* An index can be created from the MPIDR by isolating the
|
|
* significant bits at each affinity level and by shifting
|
|
* them in order to compress the 24 bits values space to a
|
|
* compressed set of values. This is equivalent to hashing
|
|
* the MPIDR through shifting and ORing. It is a collision free
|
|
* hash though not minimal since some levels might contain a number
|
|
* of CPUs that is not an exact power of 2 and their bit
|
|
* representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
|
|
*/
|
|
mpidr_hash.shift_aff[0] = fs[0];
|
|
mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
|
|
mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
|
|
(bits[1] + bits[0]);
|
|
mpidr_hash.mask = mask;
|
|
mpidr_hash.bits = bits[2] + bits[1] + bits[0];
|
|
pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
|
|
mpidr_hash.shift_aff[0],
|
|
mpidr_hash.shift_aff[1],
|
|
mpidr_hash.shift_aff[2],
|
|
mpidr_hash.mask,
|
|
mpidr_hash.bits);
|
|
/*
|
|
* 4x is an arbitrary value used to warn on a hash table much bigger
|
|
* than expected on most systems.
|
|
*/
|
|
if (mpidr_hash_size() > 4 * num_possible_cpus())
|
|
pr_warn("Large number of MPIDR hash buckets detected\n");
|
|
sync_cache_w(&mpidr_hash);
|
|
}
|
|
#endif
|
|
|
|
static void __init setup_processor(void)
|
|
{
|
|
struct proc_info_list *list;
|
|
|
|
/*
|
|
* locate processor in the list of supported processor
|
|
* types. The linker builds this table for us from the
|
|
* entries in arch/arm/mm/proc-*.S
|
|
*/
|
|
list = lookup_processor_type(read_cpuid_id());
|
|
if (!list) {
|
|
pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
|
|
read_cpuid_id());
|
|
while (1);
|
|
}
|
|
|
|
cpu_name = list->cpu_name;
|
|
__cpu_architecture = __get_cpu_architecture();
|
|
|
|
#ifdef MULTI_CPU
|
|
processor = *list->proc;
|
|
#endif
|
|
#ifdef MULTI_TLB
|
|
cpu_tlb = *list->tlb;
|
|
#endif
|
|
#ifdef MULTI_USER
|
|
cpu_user = *list->user;
|
|
#endif
|
|
#ifdef MULTI_CACHE
|
|
cpu_cache = *list->cache;
|
|
#endif
|
|
|
|
pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
|
|
cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
|
|
proc_arch[cpu_architecture()], get_cr());
|
|
|
|
snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
|
|
list->arch_name, ENDIANNESS);
|
|
snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
|
|
list->elf_name, ENDIANNESS);
|
|
elf_hwcap = list->elf_hwcap;
|
|
|
|
cpuid_init_hwcaps();
|
|
|
|
#ifndef CONFIG_ARM_THUMB
|
|
elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
|
|
#endif
|
|
#ifdef CONFIG_MMU
|
|
init_default_cache_policy(list->__cpu_mm_mmu_flags);
|
|
#endif
|
|
erratum_a15_798181_init();
|
|
|
|
elf_hwcap_fixup();
|
|
|
|
cacheid_init();
|
|
cpu_init();
|
|
}
|
|
|
|
void __init dump_machine_table(void)
|
|
{
|
|
const struct machine_desc *p;
|
|
|
|
early_print("Available machine support:\n\nID (hex)\tNAME\n");
|
|
for_each_machine_desc(p)
|
|
early_print("%08x\t%s\n", p->nr, p->name);
|
|
|
|
early_print("\nPlease check your kernel config and/or bootloader.\n");
|
|
|
|
while (true)
|
|
/* can't use cpu_relax() here as it may require MMU setup */;
|
|
}
|
|
|
|
int __init arm_add_memory(u64 start, u64 size)
|
|
{
|
|
u64 aligned_start;
|
|
|
|
/*
|
|
* Ensure that start/size are aligned to a page boundary.
|
|
* Size is rounded down, start is rounded up.
|
|
*/
|
|
aligned_start = PAGE_ALIGN(start);
|
|
if (aligned_start > start + size)
|
|
size = 0;
|
|
else
|
|
size -= aligned_start - start;
|
|
|
|
#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
|
|
if (aligned_start > ULONG_MAX) {
|
|
pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
|
|
(long long)start);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (aligned_start + size > ULONG_MAX) {
|
|
pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
|
|
(long long)start);
|
|
/*
|
|
* To ensure bank->start + bank->size is representable in
|
|
* 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
|
|
* This means we lose a page after masking.
|
|
*/
|
|
size = ULONG_MAX - aligned_start;
|
|
}
|
|
#endif
|
|
|
|
if (aligned_start < PHYS_OFFSET) {
|
|
if (aligned_start + size <= PHYS_OFFSET) {
|
|
pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
|
|
aligned_start, aligned_start + size);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
|
|
aligned_start, (u64)PHYS_OFFSET);
|
|
|
|
size -= PHYS_OFFSET - aligned_start;
|
|
aligned_start = PHYS_OFFSET;
|
|
}
|
|
|
|
start = aligned_start;
|
|
size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
|
|
|
|
/*
|
|
* Check whether this memory region has non-zero size or
|
|
* invalid node number.
|
|
*/
|
|
if (size == 0)
|
|
return -EINVAL;
|
|
|
|
memblock_add(start, size);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Pick out the memory size. We look for mem=size@start,
|
|
* where start and size are "size[KkMm]"
|
|
*/
|
|
|
|
static int __init early_mem(char *p)
|
|
{
|
|
static int usermem __initdata = 0;
|
|
u64 size;
|
|
u64 start;
|
|
char *endp;
|
|
|
|
/*
|
|
* If the user specifies memory size, we
|
|
* blow away any automatically generated
|
|
* size.
|
|
*/
|
|
if (usermem == 0) {
|
|
usermem = 1;
|
|
memblock_remove(memblock_start_of_DRAM(),
|
|
memblock_end_of_DRAM() - memblock_start_of_DRAM());
|
|
}
|
|
|
|
start = PHYS_OFFSET;
|
|
size = memparse(p, &endp);
|
|
if (*endp == '@')
|
|
start = memparse(endp + 1, NULL);
|
|
|
|
arm_add_memory(start, size);
|
|
|
|
return 0;
|
|
}
|
|
early_param("mem", early_mem);
|
|
|
|
static void __init request_standard_resources(const struct machine_desc *mdesc)
|
|
{
|
|
struct memblock_region *region;
|
|
struct resource *res;
|
|
|
|
kernel_code.start = virt_to_phys(_text);
|
|
kernel_code.end = virt_to_phys(_etext - 1);
|
|
kernel_data.start = virt_to_phys(_sdata);
|
|
kernel_data.end = virt_to_phys(_end - 1);
|
|
|
|
for_each_memblock(memory, region) {
|
|
res = memblock_virt_alloc(sizeof(*res), 0);
|
|
res->name = "System RAM";
|
|
res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
|
|
res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
|
|
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
|
|
|
request_resource(&iomem_resource, res);
|
|
|
|
if (kernel_code.start >= res->start &&
|
|
kernel_code.end <= res->end)
|
|
request_resource(res, &kernel_code);
|
|
if (kernel_data.start >= res->start &&
|
|
kernel_data.end <= res->end)
|
|
request_resource(res, &kernel_data);
|
|
}
|
|
|
|
if (mdesc->video_start) {
|
|
video_ram.start = mdesc->video_start;
|
|
video_ram.end = mdesc->video_end;
|
|
request_resource(&iomem_resource, &video_ram);
|
|
}
|
|
|
|
/*
|
|
* Some machines don't have the possibility of ever
|
|
* possessing lp0, lp1 or lp2
|
|
*/
|
|
if (mdesc->reserve_lp0)
|
|
request_resource(&ioport_resource, &lp0);
|
|
if (mdesc->reserve_lp1)
|
|
request_resource(&ioport_resource, &lp1);
|
|
if (mdesc->reserve_lp2)
|
|
request_resource(&ioport_resource, &lp2);
|
|
}
|
|
|
|
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
|
|
struct screen_info screen_info = {
|
|
.orig_video_lines = 30,
|
|
.orig_video_cols = 80,
|
|
.orig_video_mode = 0,
|
|
.orig_video_ega_bx = 0,
|
|
.orig_video_isVGA = 1,
|
|
.orig_video_points = 8
|
|
};
|
|
#endif
|
|
|
|
static int __init customize_machine(void)
|
|
{
|
|
/*
|
|
* customizes platform devices, or adds new ones
|
|
* On DT based machines, we fall back to populating the
|
|
* machine from the device tree, if no callback is provided,
|
|
* otherwise we would always need an init_machine callback.
|
|
*/
|
|
of_iommu_init();
|
|
if (machine_desc->init_machine)
|
|
machine_desc->init_machine();
|
|
#ifdef CONFIG_OF
|
|
else
|
|
of_platform_populate(NULL, of_default_bus_match_table,
|
|
NULL, NULL);
|
|
#endif
|
|
return 0;
|
|
}
|
|
arch_initcall(customize_machine);
|
|
|
|
static int __init init_machine_late(void)
|
|
{
|
|
struct device_node *root;
|
|
int ret;
|
|
|
|
if (machine_desc->init_late)
|
|
machine_desc->init_late();
|
|
|
|
root = of_find_node_by_path("/");
|
|
if (root) {
|
|
ret = of_property_read_string(root, "serial-number",
|
|
&system_serial);
|
|
if (ret)
|
|
system_serial = NULL;
|
|
}
|
|
|
|
if (!system_serial)
|
|
system_serial = kasprintf(GFP_KERNEL, "%08x%08x",
|
|
system_serial_high,
|
|
system_serial_low);
|
|
|
|
return 0;
|
|
}
|
|
late_initcall(init_machine_late);
|
|
|
|
#ifdef CONFIG_KEXEC
|
|
static inline unsigned long long get_total_mem(void)
|
|
{
|
|
unsigned long total;
|
|
|
|
total = max_low_pfn - min_low_pfn;
|
|
return total << PAGE_SHIFT;
|
|
}
|
|
|
|
/**
|
|
* reserve_crashkernel() - reserves memory are for crash kernel
|
|
*
|
|
* This function reserves memory area given in "crashkernel=" kernel command
|
|
* line parameter. The memory reserved is used by a dump capture kernel when
|
|
* primary kernel is crashing.
|
|
*/
|
|
static void __init reserve_crashkernel(void)
|
|
{
|
|
unsigned long long crash_size, crash_base;
|
|
unsigned long long total_mem;
|
|
int ret;
|
|
|
|
total_mem = get_total_mem();
|
|
ret = parse_crashkernel(boot_command_line, total_mem,
|
|
&crash_size, &crash_base);
|
|
if (ret)
|
|
return;
|
|
|
|
ret = memblock_reserve(crash_base, crash_size);
|
|
if (ret < 0) {
|
|
pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
|
|
(unsigned long)crash_base);
|
|
return;
|
|
}
|
|
|
|
pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
|
|
(unsigned long)(crash_size >> 20),
|
|
(unsigned long)(crash_base >> 20),
|
|
(unsigned long)(total_mem >> 20));
|
|
|
|
crashk_res.start = crash_base;
|
|
crashk_res.end = crash_base + crash_size - 1;
|
|
insert_resource(&iomem_resource, &crashk_res);
|
|
}
|
|
#else
|
|
static inline void reserve_crashkernel(void) {}
|
|
#endif /* CONFIG_KEXEC */
|
|
|
|
void __init hyp_mode_check(void)
|
|
{
|
|
#ifdef CONFIG_ARM_VIRT_EXT
|
|
sync_boot_mode();
|
|
|
|
if (is_hyp_mode_available()) {
|
|
pr_info("CPU: All CPU(s) started in HYP mode.\n");
|
|
pr_info("CPU: Virtualization extensions available.\n");
|
|
} else if (is_hyp_mode_mismatched()) {
|
|
pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
|
|
__boot_cpu_mode & MODE_MASK);
|
|
pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
|
|
} else
|
|
pr_info("CPU: All CPU(s) started in SVC mode.\n");
|
|
#endif
|
|
}
|
|
|
|
void __init setup_arch(char **cmdline_p)
|
|
{
|
|
const struct machine_desc *mdesc;
|
|
|
|
setup_processor();
|
|
mdesc = setup_machine_fdt(__atags_pointer);
|
|
if (!mdesc)
|
|
mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
|
|
machine_desc = mdesc;
|
|
machine_name = mdesc->name;
|
|
dump_stack_set_arch_desc("%s", mdesc->name);
|
|
|
|
if (mdesc->reboot_mode != REBOOT_HARD)
|
|
reboot_mode = mdesc->reboot_mode;
|
|
|
|
init_mm.start_code = (unsigned long) _text;
|
|
init_mm.end_code = (unsigned long) _etext;
|
|
init_mm.end_data = (unsigned long) _edata;
|
|
init_mm.brk = (unsigned long) _end;
|
|
|
|
/* populate cmd_line too for later use, preserving boot_command_line */
|
|
strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
|
|
*cmdline_p = cmd_line;
|
|
|
|
if (IS_ENABLED(CONFIG_FIX_EARLYCON_MEM))
|
|
early_fixmap_init();
|
|
|
|
parse_early_param();
|
|
|
|
#ifdef CONFIG_MMU
|
|
early_paging_init(mdesc);
|
|
#endif
|
|
setup_dma_zone(mdesc);
|
|
sanity_check_meminfo();
|
|
arm_memblock_init(mdesc);
|
|
|
|
paging_init(mdesc);
|
|
request_standard_resources(mdesc);
|
|
|
|
if (mdesc->restart)
|
|
arm_pm_restart = mdesc->restart;
|
|
|
|
unflatten_device_tree();
|
|
|
|
arm_dt_init_cpu_maps();
|
|
psci_dt_init();
|
|
xen_early_init();
|
|
#ifdef CONFIG_SMP
|
|
if (is_smp()) {
|
|
if (!mdesc->smp_init || !mdesc->smp_init()) {
|
|
if (psci_smp_available())
|
|
smp_set_ops(&psci_smp_ops);
|
|
else if (mdesc->smp)
|
|
smp_set_ops(mdesc->smp);
|
|
}
|
|
smp_init_cpus();
|
|
smp_build_mpidr_hash();
|
|
}
|
|
#endif
|
|
|
|
if (!is_smp())
|
|
hyp_mode_check();
|
|
|
|
reserve_crashkernel();
|
|
|
|
#ifdef CONFIG_MULTI_IRQ_HANDLER
|
|
handle_arch_irq = mdesc->handle_irq;
|
|
#endif
|
|
|
|
#ifdef CONFIG_VT
|
|
#if defined(CONFIG_VGA_CONSOLE)
|
|
conswitchp = &vga_con;
|
|
#elif defined(CONFIG_DUMMY_CONSOLE)
|
|
conswitchp = &dummy_con;
|
|
#endif
|
|
#endif
|
|
|
|
if (mdesc->init_early)
|
|
mdesc->init_early();
|
|
}
|
|
|
|
|
|
static int __init topology_init(void)
|
|
{
|
|
int cpu;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
|
|
cpuinfo->cpu.hotpluggable = platform_can_hotplug_cpu(cpu);
|
|
register_cpu(&cpuinfo->cpu, cpu);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
subsys_initcall(topology_init);
|
|
|
|
#ifdef CONFIG_HAVE_PROC_CPU
|
|
static int __init proc_cpu_init(void)
|
|
{
|
|
struct proc_dir_entry *res;
|
|
|
|
res = proc_mkdir("cpu", NULL);
|
|
if (!res)
|
|
return -ENOMEM;
|
|
return 0;
|
|
}
|
|
fs_initcall(proc_cpu_init);
|
|
#endif
|
|
|
|
static const char *hwcap_str[] = {
|
|
"swp",
|
|
"half",
|
|
"thumb",
|
|
"26bit",
|
|
"fastmult",
|
|
"fpa",
|
|
"vfp",
|
|
"edsp",
|
|
"java",
|
|
"iwmmxt",
|
|
"crunch",
|
|
"thumbee",
|
|
"neon",
|
|
"vfpv3",
|
|
"vfpv3d16",
|
|
"tls",
|
|
"vfpv4",
|
|
"idiva",
|
|
"idivt",
|
|
"vfpd32",
|
|
"lpae",
|
|
"evtstrm",
|
|
NULL
|
|
};
|
|
|
|
static const char *hwcap2_str[] = {
|
|
"aes",
|
|
"pmull",
|
|
"sha1",
|
|
"sha2",
|
|
"crc32",
|
|
NULL
|
|
};
|
|
|
|
static int c_show(struct seq_file *m, void *v)
|
|
{
|
|
int i, j;
|
|
u32 cpuid;
|
|
|
|
for_each_online_cpu(i) {
|
|
/*
|
|
* glibc reads /proc/cpuinfo to determine the number of
|
|
* online processors, looking for lines beginning with
|
|
* "processor". Give glibc what it expects.
|
|
*/
|
|
seq_printf(m, "processor\t: %d\n", i);
|
|
cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
|
|
seq_printf(m, "model name\t: %s rev %d (%s)\n",
|
|
cpu_name, cpuid & 15, elf_platform);
|
|
|
|
#if defined(CONFIG_SMP)
|
|
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
|
|
per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
|
|
(per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
|
|
#else
|
|
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
|
|
loops_per_jiffy / (500000/HZ),
|
|
(loops_per_jiffy / (5000/HZ)) % 100);
|
|
#endif
|
|
/* dump out the processor features */
|
|
seq_puts(m, "Features\t: ");
|
|
|
|
for (j = 0; hwcap_str[j]; j++)
|
|
if (elf_hwcap & (1 << j))
|
|
seq_printf(m, "%s ", hwcap_str[j]);
|
|
|
|
for (j = 0; hwcap2_str[j]; j++)
|
|
if (elf_hwcap2 & (1 << j))
|
|
seq_printf(m, "%s ", hwcap2_str[j]);
|
|
|
|
seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
|
|
seq_printf(m, "CPU architecture: %s\n",
|
|
proc_arch[cpu_architecture()]);
|
|
|
|
if ((cpuid & 0x0008f000) == 0x00000000) {
|
|
/* pre-ARM7 */
|
|
seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
|
|
} else {
|
|
if ((cpuid & 0x0008f000) == 0x00007000) {
|
|
/* ARM7 */
|
|
seq_printf(m, "CPU variant\t: 0x%02x\n",
|
|
(cpuid >> 16) & 127);
|
|
} else {
|
|
/* post-ARM7 */
|
|
seq_printf(m, "CPU variant\t: 0x%x\n",
|
|
(cpuid >> 20) & 15);
|
|
}
|
|
seq_printf(m, "CPU part\t: 0x%03x\n",
|
|
(cpuid >> 4) & 0xfff);
|
|
}
|
|
seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
|
|
}
|
|
|
|
seq_printf(m, "Hardware\t: %s\n", machine_name);
|
|
seq_printf(m, "Revision\t: %04x\n", system_rev);
|
|
seq_printf(m, "Serial\t\t: %s\n", system_serial);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void *c_start(struct seq_file *m, loff_t *pos)
|
|
{
|
|
return *pos < 1 ? (void *)1 : NULL;
|
|
}
|
|
|
|
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
|
{
|
|
++*pos;
|
|
return NULL;
|
|
}
|
|
|
|
static void c_stop(struct seq_file *m, void *v)
|
|
{
|
|
}
|
|
|
|
const struct seq_operations cpuinfo_op = {
|
|
.start = c_start,
|
|
.next = c_next,
|
|
.stop = c_stop,
|
|
.show = c_show
|
|
};
|