94a8cfceaa
Most upstream devs boot STi platform via JTAG which abuses the boot process by setting the PC of secondary cores directly. As a consquence, booting STi platforms via u-boot results in only the primary core being brought up as the code to manage the holding pen is not upstream. This patch adds the necessary code to bring the secondary cores out of the holding pen. It uses the cpu-release-addr DT property to get the address of the holding pen from the bootloader. With this patch booting upstream kernels via u-boot works correctly: [ 0.045456] CPU: Testing write buffer coherency: ok [ 0.045597] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.045734] Setting up static identity map for 0x40209000 - 0x40209098 [ 0.065047] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.065081] Brought up 2 CPUs [ 0.065089] SMP: Total of 2 processors activated (5983.43 BogoMIPS). [ 0.065092] CPU: All CPU(s) started in SVC mode. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
44 lines
1 KiB
ArmAsm
44 lines
1 KiB
ArmAsm
/*
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* arch/arm/mach-sti/headsmp.S
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*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* http://www.st.com
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*
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* Cloned from linux/arch/arm/mach-vexpress/headsmp.S
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*
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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/*
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* ST specific entry point for secondary CPUs. This provides
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* a "holding pen" into which all secondary cores are held until we're
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* ready for them to initialise.
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*/
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ENTRY(sti_secondary_startup)
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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add r6, r6, r4
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pen: ldr r7, [r6]
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cmp r7, r0
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(sti_secondary_startup)
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1: .long .
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.long pen_release
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