Moved all the board specific internal PHY functions out of usb_musb.c file as this file is shared between the OMAP2+ and AM35xx platforms. There exists a file which has the functions specific to internal PHY used for OMAP4 platform. Moved all phy specific functions to this file and passing these functions through board data in the board file. Signed-off-by: Hema HK <hemahk@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
242 lines
5.8 KiB
C
242 lines
5.8 KiB
C
/*
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* This file configures the internal USB PHY in OMAP4430. Used
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* with TWL6030 transceiver and MUSB on OMAP4430.
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Author: Hema HK <hemahk@ti.com>
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/usb.h>
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#include <plat/usb.h>
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#include "control.h"
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/* OMAP control module register for UTMI PHY */
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#define CONTROL_DEV_CONF 0x300
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#define PHY_PD 0x1
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#define USBOTGHS_CONTROL 0x33c
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#define AVALID BIT(0)
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#define BVALID BIT(1)
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#define VBUSVALID BIT(2)
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#define SESSEND BIT(3)
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#define IDDIG BIT(4)
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static struct clk *phyclk, *clk48m, *clk32k;
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static void __iomem *ctrl_base;
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int omap4430_phy_init(struct device *dev)
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{
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ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
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if (!ctrl_base) {
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dev_err(dev, "control module ioremap failed\n");
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return -ENOMEM;
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}
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/* Power down the phy */
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__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
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phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
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if (IS_ERR(phyclk)) {
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dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
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iounmap(ctrl_base);
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return PTR_ERR(phyclk);
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}
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clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
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if (IS_ERR(clk48m)) {
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dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
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clk_put(phyclk);
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iounmap(ctrl_base);
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return PTR_ERR(clk48m);
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}
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clk32k = clk_get(dev, "usb_phy_cm_clk32k");
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if (IS_ERR(clk32k)) {
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dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
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clk_put(phyclk);
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clk_put(clk48m);
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iounmap(ctrl_base);
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return PTR_ERR(clk32k);
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}
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return 0;
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}
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int omap4430_phy_set_clk(struct device *dev, int on)
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{
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static int state;
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if (on && !state) {
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/* Enable the phy clocks */
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clk_enable(phyclk);
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clk_enable(clk48m);
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clk_enable(clk32k);
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state = 1;
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} else if (state) {
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/* Disable the phy clocks */
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clk_disable(phyclk);
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clk_disable(clk48m);
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clk_disable(clk32k);
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state = 0;
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}
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return 0;
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}
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int omap4430_phy_power(struct device *dev, int ID, int on)
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{
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if (on) {
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/* enabled the clocks */
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omap4430_phy_set_clk(dev, 1);
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/* power on the phy */
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if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
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__raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
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mdelay(200);
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}
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if (ID)
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/* enable VBUS valid, IDDIG groung */
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__raw_writel(AVALID | VBUSVALID, ctrl_base +
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USBOTGHS_CONTROL);
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else
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/*
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* Enable VBUS Valid, AValid and IDDIG
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* high impedence
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*/
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__raw_writel(IDDIG | AVALID | VBUSVALID,
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ctrl_base + USBOTGHS_CONTROL);
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} else {
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/* Enable session END and IDIG to high impedence. */
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__raw_writel(SESSEND | IDDIG, ctrl_base +
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USBOTGHS_CONTROL);
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/* Disable the clocks */
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omap4430_phy_set_clk(dev, 0);
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/* Power down the phy */
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__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
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}
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return 0;
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}
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int omap4430_phy_exit(struct device *dev)
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{
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if (ctrl_base)
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iounmap(ctrl_base);
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if (phyclk)
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clk_put(phyclk);
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if (clk48m)
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clk_put(clk48m);
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if (clk32k)
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clk_put(clk32k);
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return 0;
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}
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void am35x_musb_reset(void)
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{
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u32 regval;
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/* Reset the musb interface */
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regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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regval |= AM35XX_USBOTGSS_SW_RST;
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omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
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regval &= ~AM35XX_USBOTGSS_SW_RST;
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omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
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regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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}
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void am35x_musb_phy_power(u8 on)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(100);
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u32 devconf2;
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if (on) {
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/*
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* Start the on-chip PHY and its PLL.
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*/
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
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devconf2 |= CONF2_PHY_PLLON;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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pr_info(KERN_INFO "Waiting for PHY clock good...\n");
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while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
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& CONF2_PHYCLKGD)) {
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cpu_relax();
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if (time_after(jiffies, timeout)) {
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pr_err(KERN_ERR "musb PHY clock good timed out\n");
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break;
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}
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}
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} else {
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/*
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* Power down the on-chip PHY.
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*/
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~CONF2_PHY_PLLON;
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devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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}
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}
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void am35x_musb_clear_irq(void)
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{
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u32 regval;
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regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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regval |= AM35XX_USBOTGSS_INT_CLR;
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omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
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regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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}
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void am35x_musb_set_mode(u8 musb_mode)
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{
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u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~CONF2_OTGMODE;
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switch (musb_mode) {
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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case MUSB_HOST: /* Force VBUS valid, ID = 0 */
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devconf2 |= CONF2_FORCE_HOST;
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break;
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#endif
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#ifdef CONFIG_USB_GADGET_MUSB_HDRC
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case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
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devconf2 |= CONF2_FORCE_DEVICE;
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break;
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#endif
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#ifdef CONFIG_USB_MUSB_OTG
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case MUSB_OTG: /* Don't override the VBUS/ID comparators */
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devconf2 |= CONF2_NO_OVERRIDE;
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break;
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#endif
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default:
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pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
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}
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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}
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