2022-10-11 05:01:08 +02:00
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// Matrix Construct
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//
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// Copyright (C) Matrix Construct Developers, Authors & Contributors
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// Copyright (C) 2016-2022 Jason Volk <jason@zemos.net>
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice is present in all copies. The
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// full license for this software is available in the LICENSE file.
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#pragma once
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#define HAVE_IRCD_SIMT_CYCLES_H
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#if defined(__OPENCL_VERSION__)
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inline ulong
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__attribute__((always_inline))
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ircd_simt_cycles()
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{
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// Compiles but doesn't link on SPIR
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#if __has_builtin(__builtin_readcyclecounter) && !defined(__SPIR)
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return __builtin_readcyclecounter();
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#else
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return 0;
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#endif
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}
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#endif
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2022-12-01 20:22:11 +01:00
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#if defined(__OPENCL_VERSION__)
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/// Read the realtime-clock cycle counting timestamp `s_memrealtime` otherwise
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/// falls back to the default cycle counter (which defaults to zero if also not
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/// supported).
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///
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/// This is more consistent than `s_memtime` but slightly less granular; it is
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/// probably provided by a control unit rather than directly in an SIMD/ALU.
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inline ulong
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__attribute__((always_inline))
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ircd_simt_cycles_rtc()
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{
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ulong ret;
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#if defined(__AMDGCN__)
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asm volatile
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(
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"s_memrealtime %0"
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: "=s" (ret)
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);
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#else
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ret = ircd_simt_cycles();
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#endif
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return ret;
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}
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#endif
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