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ircd::simt: Add cycles_rtc() intrinsic for s_memrealtime on (AMDGCN).
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@ -24,3 +24,29 @@ ircd_simt_cycles()
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#endif
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}
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#endif
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#if defined(__OPENCL_VERSION__)
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/// Read the realtime-clock cycle counting timestamp `s_memrealtime` otherwise
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/// falls back to the default cycle counter (which defaults to zero if also not
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/// supported).
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///
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/// This is more consistent than `s_memtime` but slightly less granular; it is
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/// probably provided by a control unit rather than directly in an SIMD/ALU.
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inline ulong
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__attribute__((always_inline))
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ircd_simt_cycles_rtc()
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{
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ulong ret;
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#if defined(__AMDGCN__)
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asm volatile
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(
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"s_memrealtime %0"
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: "=s" (ret)
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);
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#else
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ret = ircd_simt_cycles();
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#endif
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return ret;
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}
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#endif
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