mirror of
https://github.com/matrix-construct/construct
synced 2024-05-20 03:43:47 +02:00
148 lines
2.9 KiB
C
148 lines
2.9 KiB
C
// Matrix Construct
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//
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// Copyright (C) Matrix Construct Developers, Authors & Contributors
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// Copyright (C) 2016-2022 Jason Volk <jason@zemos.net>
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice is present in all copies. The
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// full license for this software is available in the LICENSE file.
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#pragma once
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#define HAVE_IRCD_GPT_VECTOR_H
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#if !defined(__SIZEOF_FLOAT4__) && defined(__OPENCL_VERSION__)
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#define __SIZEOF_FLOAT4__ 16
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#endif
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#if !defined(__SIZEOF_FLOAT8__) && defined(__OPENCL_VERSION__)
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#define __SIZEOF_FLOAT8__ 32
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#endif
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#if !defined(__SIZEOF_FLOAT16__) && defined(__OPENCL_VERSION__)
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#define __SIZEOF_FLOAT16__ 64
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#endif
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#ifndef __OPENCL_VERSION__
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#define __constant
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#endif
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static __constant const uint
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ircd_gpt_context_tokens = 512, // 1024,
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ircd_gpt_vector_elems = 768,
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ircd_gpt_attn_rank = 12,
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ircd_gpt_attn_segs = 3,
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ircd_gpt_ffnn_segs = 4;
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static __constant const uint
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ircd_gpt_vector_attn_elems = ircd_gpt_vector_elems / ircd_gpt_attn_rank,
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ircd_gpt_attn_fcon_elems = ircd_gpt_vector_elems * ircd_gpt_attn_segs,
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ircd_gpt_ffnn_fcon_elems = ircd_gpt_vector_elems * ircd_gpt_ffnn_segs;
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//
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// embed vector
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//
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#if defined(__SIZEOF_FLOAT__)
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union ircd_gpt_vector
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{
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float
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elem[ircd_gpt_vector_elems],
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attn[ircd_gpt_attn_rank][ircd_gpt_vector_attn_elems];
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};
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#endif
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#if defined(__SIZEOF_FLOAT4__)
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union ircd_gpt_vector_f32x4
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{
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float4
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elem[ircd_gpt_vector_elems / 4],
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attn[ircd_gpt_attn_rank][ircd_gpt_vector_attn_elems / 4];
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union ircd_gpt_vector
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vector;
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};
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#endif
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//
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// attn qkv
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//
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#if defined(__SIZEOF_FLOAT__)
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struct ircd_gpt_attn_qkv
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{
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union ircd_gpt_vector
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qry,
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key,
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val;
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};
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#endif
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#if defined(__SIZEOF_FLOAT4__)
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struct ircd_gpt_attn_qkv_f32x4
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{
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union ircd_gpt_vector_f32x4
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qry,
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key,
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val;
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};
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#endif
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//
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// attn aperature
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//
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#if defined(__SIZEOF_FLOAT__)
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union ircd_gpt_attn_aperature
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{
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float
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fcon[ircd_gpt_attn_fcon_elems],
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proj[ircd_gpt_attn_segs][ircd_gpt_vector_elems],
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qkv[ircd_gpt_attn_segs][ircd_gpt_attn_rank][ircd_gpt_vector_attn_elems];
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union ircd_gpt_vector
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vector[ircd_gpt_attn_segs];
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};
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#endif
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#if defined(__SIZEOF_FLOAT4__)
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union ircd_gpt_attn_aperature_f32x4
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{
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float4
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fcon[ircd_gpt_attn_fcon_elems / 4],
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proj[ircd_gpt_attn_segs][ircd_gpt_vector_elems / 4],
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qkv[ircd_gpt_attn_segs][ircd_gpt_attn_rank][ircd_gpt_vector_attn_elems / 4];
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union ircd_gpt_vector_f32x4
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vector[ircd_gpt_attn_segs];
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};
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#endif
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//
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// ffnn aperature
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//
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#if defined(__SIZEOF_FLOAT__)
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union ircd_gpt_ffnn_aperature
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{
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float
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fcon[ircd_gpt_ffnn_fcon_elems],
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proj[ircd_gpt_ffnn_segs][ircd_gpt_vector_elems];
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union ircd_gpt_vector
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vector[ircd_gpt_ffnn_segs];
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};
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#endif
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#if defined(__SIZEOF_FLOAT4__)
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union ircd_gpt_ffnn_aperature_f32x4
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{
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float4
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fcon[ircd_gpt_ffnn_fcon_elems / 4],
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proj[ircd_gpt_ffnn_segs][ircd_gpt_vector_elems / 4];
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union ircd_gpt_vector_f32x4
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vector[ircd_gpt_ffnn_segs];
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};
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#endif
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